Semiconductor device and manufacturing method thereof

ABSTRACT

According to one embodiment, a first back surface of a first substrate and a second front surface of a second substrate are jointed together so as to connect a first conductor with a second conductor. The first conductor includes a portion having a diameter equal to that of a first gap formed above a first metal layer in a range between the first metal layer and a first front surface, and a portion having a diameter greater than that of the first gap and smaller than an outer diameter of the first metal layer in a range between the first metal layer and the first back surface. A first insulating layer has a gap formed above the first metal layer, the gap being greater than the first gap and smaller than the outer diameter of the first metal layer.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority fromJapanese Patent Application No. 2011-82951, filed on Apr. 4, 2011; theentire contents of which are incorporated herein by reference.

FIELD

Embodiments described herein relate generally to a semiconductor deviceand a manufacturing method thereof.

BACKGROUND

Along with the recent demand for miniaturization of personal digitalassistances, storage devices, and the like, there has been an increasingdemand for mounting of a plurality of semiconductor chips with highdensity. Under such circumstances, a structure having a plurality ofsemiconductor chips stacked therein has been studied. For example, asemiconductor module is manufactured in such a manner that anoperational test is performed on each semiconductor chip in the state ofa semiconductor wafer so as to select non-defective chips, and thenon-defective chips are stacked. Typically, each chip has a through viahole, connecting pads formed on the top surface of the chip, andconnecting bumps formed on the bottom surface of the chip. The bumpsformed on an upper chip are connected to the pads formed on a lowerchip, thereby electrically connecting the upper and lower chips.

However, the use of bumps to connect semiconductor chips results in anincrease in connection pitch. Additionally, it is necessary to ensure acertain thickness of each chip for handling the connection between bumpsand pads. These circumstances hinder a reduction in the thickness of thesemiconductor module. Furthermore, an increase in the number of stackedchips may cause deterioration in the throughput of the stacking processand in the connection yield.

On the other hand, there is another method of manufacturing asemiconductor module in which semiconductor wafers are joined togetherand are then divided into chips. In this method, bumps for providingelectrical connection between wafers can be omitted. This results insolving the above-mentioned problems which may be caused when bumps areused.

When the method of dividing the joined semiconductor wafers into chipsis employed, it is impossible to select only non-defective semiconductorchips to be stacked. Accordingly, the method requires a countermeasurefor avoiding the situation in which a failure occurs in the entiresemiconductor module when a defective semiconductor chip is present. Thesituation in which a failure occurs in the entire semiconductor modulecan be avoided in the following manner, for example. That is, a trimmingregion is formed in advance for each of wiring lines connected to a vialand, and if a defective chip is found, a laser beam is applied to thetrimming region to disconnect the corresponding wiring line.

However, an increase in the number of disconnected wiring lines leads toan increase in the trimming region. This may result in limitation of thedegree of freedom of design and deterioration in the throughput.Additionally, other problems such as a cutting failure due toinsufficient welding of wiring lines, a short-circuit failure due toscattering of a metal material of wiring lines, and a lack of cuttingstability due to difficulty in controlling the shape of a cut portionmay occur. Especially in the case of using a copper wiring line, thedifficulty in welding and cutting increases, which makes these problemsmore significant.

To join semiconductor wafers together, an effective structure ormanufacturing process for ensuring electrical connection between viaholes that penetrate wafers and semiconductor elements formed on eachwafer and for ensuring electrical connection with external parts has notbeen established yet.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic plan view illustrating a configuration in thevicinity of a via land according to an embodiment;

FIGS. 2 to 11 are sectional views schematically illustrating anexemplary process of the manufacturing method of a semiconductor deviceaccording to the first embodiment;

FIG. 12 is a schematic diagram illustrating a semiconductor moduleaccording to a second embodiment; and

FIG. 13 is a schematic plan view of a semiconductor device including avia land having another shape.

DETAILED DESCRIPTION

In general, according to one embodiment, a first substrate includes afirst semiconductor element provided above a first front surface of thefirst substrate; a first metal layer electrically connected to the firstsemiconductor element and having a first gap above the first frontsurface of the first substrate; and a first insulating layer formedabove each of the first metal layer and the first front surface. Thefirst substrate also includes a first conductor embedded in a first viahole at a forming position of the first metal layer, the first via holepenetrating the first substrate in a thickness direction thereof. Asecond substrate includes a second semiconductor element provided abovea second front surface of the second substrate; and a second conductorembedded in a second via hole penetrating the second substrate in athickness direction thereof. A first back surface opposed to the firstfront surface of the first substrate and the second front surface of thesecond substrate are joined together so as to connect the firstconductor with the second conductor. The first conductor includes afirst portion having a diameter equal to that of the first gap in arange between the first metal layer and the first front surface; and asecond portion having a diameter greater than that of the first gap andsmaller than an outer diameter of the first metal layer in a rangebetween the first metal layer and the first back surface. The firstinsulating layer has a gap formed above the first metal layer, the gapbeing greater than the first gap and smaller than the outer diameter ofthe first metal layer.

Exemplary embodiments of a semiconductor device and a manufacturingmethod thereof will be explained below in detail with reference to theaccompanying drawings. The present invention is not limited to thefollowing embodiments.

FIRST EMBODIMENT

A semiconductor device and a manufacturing method thereof according to afirst embodiment will be described with reference to the drawings. FIG.1 is a schematic plan view of a via land according to the firstembodiment. FIGS. 2 to 11 are sectional views each schematicallyillustrating an exemplary process of the manufacturing method of asemiconductor device according to the first embodiment. As illustratedin FIG. 2, insulating layers 12 and 14 are formed on a semiconductorwafer 10, and a via land 16 made of metal (for example, copper) isformed on the insulating layer 12. The via land 16 has a doughnut shapein plan view (in a direction perpendicular to the principal surface ofthe semiconductor wafer 10), and the insulating layer 12 formed belowthe via land 16 is exposed at a central portion. The via land 16 isconnected to a metal wiring line (hereinafter referred to as “wiringline”) 18 at an end portion. The wiring line 18 is connected to asemiconductor element not illustrated (for example, a semiconductormemory such as a flash memory or a DRAM (Dynamic Random Access Memory)).As illustrated in FIG. 1, the insulating layer 14 is formed in a regionat a predetermined distance or further from the center of the land sothat a portion (a portion in the range from the land center to thepredetermined distance) of the via land 16 is exposed. Herein, Arepresents the outer diameter of the via land 16; B represents the outerdiameter of a portion of the via land 16 which is not, covered by theinsulating layer 14 (an opening diameter of the insulating layer 14);and C represents the inner diameter of the via land 16 (diameterexcluding the via land). In the structure as described above, therelation of A>B>C is maintained. For example, A is 20 μm; B is 14 μm;and C is 7 μm.

A plurality of chips (for example, about more than 700 chips for a waferof 300 mm) is formed on the semiconductor wafer 10, and each chip hasthe structure of the via land 16 as illustrated in FIGS. 1 and 2. In thestate of the semiconductor wafer 10, an operational test is performed oneach chip with a test device such as a probe card. Thus, defectivesemiconductor chips are specified, which makes it possible to createdrawing data, which is called a wafer map, representing the positions ofthe defective chips on the semiconductor wafer 10.

Next, as illustrated in FIG. 3, an etchant 71 is applied onto the vialand 16 of a defective chip. As a result, the exposed portion of the vialand 16 is removed. In the manner as described above, the semiconductorwafer 10 in which a part of the via land of each defective chip isremoved can be obtained.

Then, the semiconductor wafer 10 is stacked with a second wafer 0serving as a base substrate. The semiconductor wafer 0 has a number ofconnecting pads 2 corresponding to the number of the via lands 16. Thesemiconductor wafer 0 and the semiconductor wafer 10 are joined togetherin the state where the connecting pads 2 of the semiconductor wafer 0are aligned so as to be positioned immediately above the via land 16which is provided on each chip of the semiconductor wafer 10. In thefirst embodiment, an adhesive layer 6 is used to join the semiconductorwafers 0 and 10 together. Alternatively, the semiconductor wafers 0 and10 may be directly joined together without using the adhesive layer 6.More alternatively, a layer such as an insulating layer may be formed oneither one or both of the semiconductor wafer 0 and the semiconductorwafer 10, and the semiconductor wafers 0 and 10 may be joined togetherthrough the insulating layer or the like. For example, an insulatinglayer for covering the insulating layer 14 and the via land 16 may befurther formed. At this time, the combined thickness of the wafer 0 andthe wafer 10 is 775 μm, for example.

After that, in the state where the semiconductor wafer 0 is held, theback surface of the semiconductor wafer 10 is ground and polished to athickness of 20 μm. At this time, since the semiconductor wafer 10 isjoined with the semiconductor wafer 0, the rigidity to withstand thepolishing can be ensured. After the polishing, an insulating layer 17 isformed on the back surface (polished surface) of the semiconductor wafer10 as illustrated in FIG. 4.

A resist pattern (not illustrated) is formed on the back surface using awell-known technique and dry etching is then performed, thereby forminga via hole 15. The cross-section of the via hole 15 taken along thedirection in parallel with the principal surface of the semiconductorwafer 10 has a substantially circular shape in the first embodiment. Thecenter of the cross-section substantially coincides with the center ofthe via land 16 in plan view, and an inner diameter D (for example, 10μm) of the cross-section satisfies the relation of A>D>C (A representsthe outer diameter of the via land 16; C represents the inner diameter(diameter excluding the via land) of the via land 16; and D representsthe inner diameter of the via hole 15). Accordingly, during the etchingprocess for forming the via hole 15 penetrating the wafer 10, the vialand 16 serves as a mask for inhibiting etching after a portion in therange from the back surface to the via land 16 of the wafer (includingthe insulating layers 17 and 12) is etched. Etching is continuouslycarried out through a gap portion of the via land 16 which is notblocked by the via land 16. Etching is continued until the adhesivelayer 6 is etched to reach the electrode pads 2 of the semiconductorwafer 0.

The via hole 15 thus formed has steps formed at positions correspondingto the via lands 16 as illustrated in FIG. 5. This results in formationof two regions: a large diameter region ranging from the back surface ofthe semiconductor wafer 10 to the via land 16; and a small diameterregion ranging from the via land 16 to the electrode pad 2 of thesemiconductor wafer 0. In this case, the surface, which faces the backsurface of the semiconductor wafer 10, of each of a part of theelectrode pad 2 and a part of the via land 16 is exposed. If etching isperformed such that the side surfaces of the via hole 15 aresubstantially perpendicular to the semiconductor wafer 10, the exposedportion of the electrode pad 2 has a diameter of about 7 μm and theexposed portion of the via land 16 has a diameter of about 10 μm (inthis case, however, the via land 16 has a doughnut shape with an innerdiameter of about 7 μm). Accordingly, the exposed area of the electrodepad 2 is substantially equal to the exposed area of the via land 16.

After that, an insulating film 13 is formed on the inner wall of the viahole 15. Then, as illustrated in FIG. 6, the insulation film 13 formedon the surface facing the back surface of the semiconductor wafer 10 isremoved by RIE (Reactive Ion Etching), so that the insulating film 13remains only on the side walls of the via hole 15.

Further, a plating seed layer is formed within the via hole 15, asneeded, and copper plating is carried out using the semiconductor wafer0 as a plating electrode. As illustrated in FIG. 7, a metal 11 (forexample, copper) is filled in the via hole 15. Because the via hole 15is formed in each chip region, the plating is performed in the statewhere the plurality of via holes 15 is electrically connected inparallel to the semiconductor wafer 0. The use of the semiconductorwafer 0 as an electrode enables bottom-up filling, reduction of a voidfailure, and improvement in uniformity of the plating between the viaholes 15 in the semiconductor wafer 10. Additionally, even if the viaholes have a high aspect ratio, the filling property can be improved.

As a result, the surface of the via land 16 which faces the back surfaceside of the semiconductor wafer 10 is electrically connected to themetal 11 formed in the via hole 15. At the same time, the surface of theelectrode pad 2 which faces the back surface side of the wafer 10 iselectrically connected to the metal 11 formed in the via hole 15.Further, the exposed area of the via land 16 is substantially equal tothe exposed area of the electrode pad 2, which makes it possible tosatisfactorily maintain the electrical connection between the exposedportions and the metal 11 formed in the via hole.

After that, the same processes are repeated. Specifically, asemiconductor element and a via land 26 are formed on each chip regionof another semiconductor wafer 20, and a failure test is then performed.As illustrated in FIG. 3, a predetermined wiring line is removed in eachdefective chip. After that, as illustrated in FIG. 8, the elementsurface of the semiconductor wafer 20 and the back surface (polishedsurface) of the semiconductor wafer 10 are joined together using anadhesive layer 72. Then, the back surface of the semiconductor wafer 20is polished to thereby thin the semiconductor wafer 20 to a thickness of20 μm. An insulating film 23 is formed on the polished surface, andetching is then performed on the back surface of the semiconductor wafer20 to thereby form a via hole 25. The via hole 25 has a diameter greaterthan that of the gap of the via land 26, and the via hole 25 is formedsuch that the center of the via hole 25 substantially coincides with thecenter of the via land 26 in plan view. Thus, the via hole 25 has alarge diameter portion ranging from the back surface of thesemiconductor wafer 20 to the via land 26, and a small diameter portionranging from the via land 26 to the metal 11 formed in the via hole 15.During the etching process, the back surface of the semiconductor wafer10 and the front surface of the semiconductor wafer 20 are joinedtogether through the adhesive layer 72. Accordingly, not only thesemiconductor wafer 20 but also the adhesive layer 72 is etched toexpose the metal 11 of the semiconductor wafer 10. In the manner asdescribed above, the via hole 25 penetrating the semiconductor wafer 20is formed. After formation of the insulating film 23 on the side walls,a metal 21 is filled in the via hole 25 using the semiconductor wafer 0as a plating electrode (FIG. 8).

FIG. 9 illustrates a structure in which semiconductor wafers 0, 10, 20,30, 40 are stacked (components of the structure are illustrated in otherfigures, so reference numerals and explanation thereof are omitted). Inthis case, however, it has turned out as a result of a test that thesemiconductor wafer 20 includes defective chips at illustratedpositions. For this reason, a part of the via land is removed using anetchant in the manner as described above, and the other semiconductorwafers 10 and 30 are then stacked. This allows the process for the viahole to be finished without being inhibited by the via land, duringformation of the via hole in the semiconductor wafer 20. As a result,the chip in the semiconductor wafer 20 and the conductor formed in thevia hole are electrically disconnected.

After that, as illustrated in FIG. 10, the front surface of thesemiconductor wafer 0 is ground and polished to expose the connectingpads 2 (electrodes). The structure in which the semiconductor wafers 10to 40 are stacked has a thickness of 80 μm. Accordingly, if thestructure is held or clamped during the polishing of the semiconductorwafer 0, the semiconductor wafer 0 can be suitably polished. This makesit possible to manufacture a structure including a via hole penetratingthe entire structure and conductor portions (connecting pads 2 andconductor exposed to the back surface of the semiconductor wafer 40)which are electrically connected to the via hole and exposed to thefront and back surfaces of the structure.

After that, the stacked layer structure of the semiconductor wafer isdivided into chips by a well-known technique such as dicing or scribing.As a result of polishing and removing an upper portion of thesemiconductor wafer 0, the stacked layer structure has a thickness of 80μm or more. This enables favorable division.

FIG. 11 illustrates a structure in which semiconductor modules 100-1 and100-2 which are formed in the manner as described above are stackedthrough bumps 50. In the structure illustrated in FIG. 11, the twosemiconductor modules 100-1 and 100-2 are each formed by stacking foursemiconductor substrates. Alternatively, modules having different numberof substrates to be stacked (for example, five layers or three layers)may be stacked. For example, when a semiconductor module having a4-layer structure includes a defective semiconductor chip, thesemiconductor module may be stacked with a semiconductor module having a5-layer structure. On the other hand, when the semiconductor modulehaving the 4-layer structure includes no defective semiconductor chip,the semiconductor module is further stacked with a semiconductor modulehaving the 4-layer structure. Thus, the stack of semiconductor moduleshaving different layer structures depending on the presence or absenceof a defective chip enables adjustment of the entire memory capacity tobe maintained constant.

SECOND EMBODIMENT

FIG. 12 is a schematic diagram of a semiconductor module according to asecond embodiment. As for components fulfilling the same functions asthose of the semiconductor module illustrated in the first embodiment,reference numerals and explanation thereof are omitted.

Generally, via holes (and conductor formed therein) are used for asignal line, a ground line, a power supply line, and the like. In somecases, there is no need to expose electrodes to the front surface of asemiconductor module, depending on the intended use. In this case, asillustrated in FIG. 12, a via land 52 in the semiconductor wafer 10 mayhave a structure with no gap. Insulating layers 54 and 56 are formed onthe via land 52. In this case, the following process can be employed.That is, a transparent base substrate, such as glass, is prepared inplace of the semiconductor wafer 0 and the base substrate and the frontsurface of the semiconductor wafer 10 are temporarily joined togetherusing an adhesive layer, which makes it possible to polish the backsurface of the semiconductor wafer 10. Then, as in the first embodiment,the plurality of joined semiconductor wafers is subjected to heattreatment and other treatments, and the entirety of the semiconductorwafer 10 and the base substrate is separated and removed. This leads toa reduction in cost of the semiconductor wafer 0. It is also possible toemploy a structure in which an electrode to be electrically connected toa via hole is provided on the semiconductor wafer 10 and the electrodeis exposed to the front surface after the base substrate is removed.

There has conventionally been known a method of establishing electricalconduction between substrates using a via hole upon stack of a SOI(Silicon-On-Insulator) substrate. Specifically, the front surface(element forming surface) of a wafer having a semiconductor elementformed thereon and the front surface (element forming surface) of an SOIsubstrate having a semiconductor element formed thereon are joinedtogether by oxide bonding. After that, the Si substrate formed on theback surface side of the SOI substrate is removed using an etchant toexpose an SiO₂ film (BOX film). Thereafter, a via hole is formed toobtain electrical conduction between the both elements of the SOIsubstrate and the wafer and the via hole. However, this structure isbased on the premise of using an expensive SOI substrate, resulting inlimitation of the application range. Further, joining of the elementforming surfaces may result in lowered joining yield. Furthermore, therehas been disclosed no method of forming a via hole penetrating a module(a structure having a plurality of semiconductor wafers stackedtherein). Unlike such a conventional technique, the above embodimentsare not limited to an SOI substrate and thus are widely applicable.Furthermore, in the above embodiments, the element forming surfaces arenot joined together, thereby preventing the joining yield from beinglowered. Moreover, each via hole is formed at the predetermined positionafter the wafers are joined together. This provides an advantage ofeasily forming the via hole penetrating the stacked structure even inthe case where a large number of wafers are stacked.

Note that the present invention is not limited to the above embodiment,but can be modified in various manners. For example, the number ofwafers to be stacked is not limited to four, but eight or more wafersmay be stacked. An increase in the number of wafers to be stacked mayfacilitate handling for separation or removal of a wafer or a basesubstrate.

As the base substrate which is thereafter separated or removed from thewafer structure, various materials including a semiconductor wafer and atransparent substrate such as glass may be used. In the case ofperforming a heat treatment during the separation/removal process to beperformed thereafter, however, it is necessary to select a material inconsideration of thermal expansion/contraction. It should be noted thatwhen glass or the like is used as the base substrate, it is difficult touse the base substrate as a plating electrode.

A method other than plating may be used to fill a conductor into a viahole. It is not necessary to fill the conductor in all the space withinthe via hole. For example, the conductor may be disposed conformally.

Further, it is sufficient that the relation of A (representing the outerdiameter of the via land)>B (representing the outer diameter of aportion of the via land which is not covered by the upper insulatingfilm)>C (representing the inner diameter of the via land) and therelation of A>D (representing the via hole diameter)>C are satisfied ina specific cross-section. Specifically, as for the magnitude relationbetween the gap and the diameter, it is sufficient that the magnituderelation between the gap of the metal layer in a certain cross-section(a surface perpendicular to the front surface of the substrate) and thediameter of the cross-section is ensured. It is not necessary to ensurethe magnitude relation in any cross-section. For example, provided thatthe magnitude relation in a predetermined cross-section is ensured, thegap of the metal layer or the like in the vertical cross-section may begreater than the hole diameter.

FIG. 13 is a schematic plan view of a semiconductor device including avia land having another shape. As illustrated in FIG. 13, for example, avia land 504 has a U-shape (the outline of the via land 504 covered withan upper insulating layer 510 is indicated by the dotted line). Thus, ina cross-section parallel to the lateral direction of FIG. 13, therelation of A>B>C is maintained. Meanwhile, in a cross-section parallelto the longitudinal direction (vertical direction) of FIG. 13, the vialands 504 are not provided at predetermined intervals, which makes itimpossible to define the relation among A, B, and C. In such astructure, however, if a via hole having a circular shape incross-section and having the relation of B>D>C is formed at the centerin FIG. 13, the via land functions as a mask during etching forformation of the via hole, thereby achieving an object of the presentinvention. From the same point of view, it is understood that even inthe case where wiring lines formed in parallel with each other atpredetermined intervals are used in place of the via land, for example,the same function as the via land of the second embodiment can beobtained.

More alternatively, the via hole may be formed so as to satisfy therelation A>D>B. Also in this case, electrical insulation between the viahole (conductor formed therein) and the via land is not established onlyby removing the exposed portion of the via land in a defective chip, butthe via land functions as a mask during etching for formation of the viahole. The name “via land” is used in the embodiments because a via landis provided in the middle of a through via hole and is electricallyconnected to the conductor formed in the via hole. However, the samefunction can also be obtained by using wiring lines or other metalfilms.

When the cross-section of a via hole or the like has a circular shape,the filling property of the conductor can be improved. The shape of thecross-section of each via hole is not limited to a circular shape, butmay be a rectangular shape or another shape. More alternatively, thecross-section may be tapered.

The process for forming the semiconductor element and the like may becarried out before the process for joining the wafer and the basesubstrate or after the joining process. The order of the other processescan be changed freely to the extent that can be reasonably recognized bythose skilled in the art based on the scope of the present invention.

The front surface of each substrate includes the front surface and aregion extending in the height and depth directions in the vicinity ofthe front surface. The formation of elements and the like on the frontsurface of each substrate includes formation of elements on the frontsurface and in a region in the vicinity of the front surface.

The joining of substrates includes indirect joining of substratesthrough an adhesive layer or the like. Furthermore, the case where holesare continuously formed indicates temporal continuity and includes thecase of etching both holes at once within the same chamber (withoutinhibiting a change of an etchant component). Moreover, as for theelectrical connection relation, there is no need to directly connect thecomponents. The components may be indirectly connected to each other.

While certain embodiments have been described, these embodiments havebeen presented by way of example only, and are not intended to limit thescope of the inventions. Indeed, the novel embodiments described hereinmay be embodied in a variety of other forms; furthermore, variousomissions, substitutions and changes in the form of the embodimentsdescribed herein may be made without departing from the spirit of theinventions. The accompanying claims and their equivalents are intendedto cover such forms or modifications as would fall within the scope andspirit of the inventions.

1. A semiconductor device comprising: a first substrate including: afirst semiconductor element provided above a first front surface of thefirst substrate; a first metal layer electrically connected to the firstsemiconductor element and having a first gap above the first frontsurface of the first substrate; a first insulating layer formed aboveeach of the first metal layer and the first front surface; and a firstconductor embedded in a first via hole at a forming position of thefirst metal layer, the first via hole penetrating the first substrate ina thickness direction thereof; and a second substrate including: asecond semiconductor element formed above a second front surface of thesecond substrate; and a second conductor embedded in a second via holepenetrating the second substrate in a thickness direction thereof,wherein a first back surface opposed to the first front surface of thefirst substrate and the second front surface of the second substrate arejoined together so as to connect the first conductor with the secondconductor, the first conductor includes a first portion having adiameter equal to that of the first gap in a range between the firstmetal layer and the first front surface, and a second portion having adiameter greater than that of the first gap and smaller than an outerdiameter of the first metal layer in a range between the first metallayer and the first back surface, and the first insulating layer has agap formed above the first metal layer, the gap being greater than thefirst gap and smaller than the outer diameter of the first metal layer.2. The semiconductor device according to claim 1, wherein the secondsubstrate further includes: a second metal layer formed above the secondfront surface and electrically connected to the second semiconductorelement, the second metal layer having a second gap; and a secondinsulating layer formed above each of the second metal layer and thesecond front surface, the second conductor includes a third portionhaving a diameter equal to that of the second gap in a range between thesecond metal layer and the second front surface, and a fourth portionhaving a diameter greater than that of the second gap and smaller thanan outer diameter of the second metal layer in a range between thesecond metal layer and a second back surface of the second substrate,the second back surface being opposed to the second front surface, andthe second insulating layer has a gap formed above the second metallayer, the gap being greater than the second gap and smaller than theouter diameter of the second metal layer.
 3. The semiconductor deviceaccording to claim 1, wherein the second substrate further includes: asecond metal layer formed above the second front surface andelectrically connected to the second semiconductor element, the secondmetal layer having a second gap; and a second insulating layer formedabove each of the second metal layer and the second front surface andhaving a third gap, the second conductor is disposed in the second viahole in a range between the second front surface and a second backsurface of the second substrate, the second via hole having a diametersubstantially equal to that of the first via hole, the second backsurface being opposed to the second front surface, and the third gap ofthe second insulating layer and the second gap of the second metal layerhave a diameter greater than or equal to that of the second via hole,and the second metal layer and the second conductor are electricallydisconnected.
 4. The semiconductor device according to claim 3, whereinthe second substrate is a defective chip.
 5. The semiconductor deviceaccording to claim 1, wherein the first substrate is thinned bypolishing the first back surface and is then connected to the secondsubstrate, and the second substrate is thinned by polishing the secondback surface.
 6. The semiconductor device according to claim 1, whereinthe first and second substrates each have a thickness of 50 μm or less.7. The semiconductor device according to claim 1, wherein the firstsubstrate further includes an electrode formed above a forming positionof the first conductor of the first front surface.
 8. The semiconductordevice according to claim 7, wherein a contact area between theelectrode and the first portion the first conductor is substantiallyequal to a contact area between the first metal layer and the secondportion of the first conductor.
 9. A semiconductor device comprising: afirst substrate including: a first semiconductor element provided abovea first front surface of the first substrate; a first metal layerelectrically connected to the first semiconductor element provided abovethe first front surface of the first substrate; a first insulating layerformed above each of the first metal layer and the first front surface;a first conductor embedded in a first via hole at a forming position ofthe first metal layer, the first via hole penetrating the firstsubstrate in a thickness direction thereof; and a second substrateincluding: a second semiconductor element provided above a second frontsurface of the second substrate; and a second conductor embedded in asecond via hole penetrating the second substrate in a thicknessdirection thereof, wherein a first back surface opposed to the firstfront surface of the first substrate and the second front surface of thesecond substrate are joined together so as to connect the firstconductor with the second conductor, and the first conductor hassubstantially the same diameter in a range between the first frontsurface and the first back surface.
 10. The semiconductor deviceaccording to claim 9, wherein the second substrate further includes: asecond metal layer formed above the second front surface andelectrically connected to the second semiconductor element, the secondmetal layer having a second gap; and a second insulating layer formedabove each of the second metal layer and the second front surface, thesecond conductor includes a first portion having a diameter equal tothat of the second gap in a range between the second metal layer and thesecond front surface, and a second portion having a diameter greaterthan that of the second gap and smaller than an outer diameter of thesecond metal layer in a range between the second metal layer and asecond back surface of the second substrate, the second back surfacebeing opposed to the second front surface, and the second insulatinglayer has a gap formed above the second metal layer, the gap beinggreater than the second gap and smaller than the outer diameter of thesecond metal layer.
 11. The semiconductor device according to claim 9,wherein the second substrate further includes: a second metal layerformed above the second front surface and electrically connected to thesecond semiconductor element, the second metal layer having a secondgap; and a second insulating layer formed above each of the second metallayer and the second front surface and having a third gap, the secondconductor is disposed in the second via hole in a range between thesecond front surface and a second back surface of the second substrate,the second via hole having a diameter substantially equal to that of thefirst via hole, the second back surface being opposed to the secondfront surface, and the third gap of the second insulating layer and thesecond gap of the second metal layer have a diameter greater than orequal to that of the second via hole, and the second metal layer and thesecond conductor are electrically disconnected.
 12. The semiconductordevice according to claim 11, wherein the second substrate is adefective chip.
 13. The semiconductor device according to claim 9,wherein the first substrate is thinned by polishing the first backsurface and is then connected to the second substrate, and the secondsubstrate is thinned by polishing the second back surface.
 14. Amanufacturing method of a semiconductor device comprising: forming afirst semiconductor element above a first front surface of a firstsubstrate and forming a first metal layer electrically connected to thefirst semiconductor element above the first front surface of the firstsubstrate; bonding the first front surface of the first substrate with abase substrate; polishing a first back surface of the first substrate,the first back surface being opposed to the first front surface; forminga first via hole having a predetermined diameter in the first backsurface; forming a first conductor in the first via hole so as toelectrically connect the first metal layer with the first conductor;forming a second semiconductor element above a second front surface of asecond substrate and forming a second metal layer having a first gapelectrically connected to the second semiconductor element above thesecond front surface of the second substrate; bonding the second frontsurface of the second substrate with the first back surface of the firstsubstrate; polishing a second back surface of the second substrate, thesecond back surface being opposed to the second front surface; forming asecond via hole in the second substrate so as to communicate with aforming position of the first conductor; forming a second conductor inthe second via hole; removing a part of the base substrate; and dividinga structure including at least the first substrate and the secondsubstrate joined together.
 15. The manufacturing method of asemiconductor device according to claim 14, wherein in the formation ofthe second via hole, the second substrate is etched using the secondmetal layer as a mask, the second metal layer having a diameter greaterthan that of the first gap in a range between the second back surfaceand the second metal layer and having the first gap in a range betweenthe second metal layer and the second front surface, and in theformation of the second conductor, the second conductor is connected tothe second metal layer.
 16. The manufacturing method of a semiconductordevice according to claim 14, wherein the second via hole has a diametersubstantially equal to the diameter of the first via hole, after theformation of the second metal layer, an insulating layer having a secondgap smaller than an outer diameter of the second metal layer and greaterthan the first gap is formed above the second front surface of thesecond substrate having the second metal layer formed thereon, when thesecond semiconductor element is defective, the second metal layer isetched using the insulating layer as a mask so that the first gap of thesecond metal layer and the second gap of the insulating layer have thesame diameter, after the formation of the second metal layer and beforethe bonding of the first and second substrates, and in the formation ofthe second conductor, the second conductor and the second metal layerare disconnected.
 17. The manufacturing method of a semiconductor deviceaccording to claim 14, further comprising repeating a process from theformation of the second semiconductor element and the second metal layerabove the second substrate to the formation of the second conductor,until the number of substrates to be stacked reaches a predeterminednumber.
 18. The manufacturing method of a semiconductor device accordingto claim 14, wherein the base substrate is a transparent substrate, andin the removal of the base substrate, the transparent substrate isseparated from the structure.
 19. The manufacturing method of asemiconductor device according to claim 14, wherein the first basesubstrate is one of a semiconductor substrate and a conductor substrate,and in the formation of the first conductor, the first conductor isfilled in the first via hole by plating using the base substrate as aplating electrode.
 20. The manufacturing method of a semiconductordevice according to claim 14, wherein the first and second back surfacesare polished to polish each of the first and second substrates to athickness of 50 μm or less.